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XCR3512XL: 512 Macrocell CPLD
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DS081 (v1.2) September 4, 2001
Advance Product Specification
Features
* * * * * Lowest power 512 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 512 macrocells with 12,800 usable gates Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (260 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - FZPTM CMOS design technology Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 clocks available per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for additional I/O 2.7V to 3.6V supply voltage at industrial grade voltage range Programmable slew rate control per output Security bit prevents unauthorized access Refer to XPLA3 family data sheet (DS012) for architecture description
Description
The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 32 function blocks provide 12,800 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz.
TotalCMOSTM Design Technique for Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3512XL TotalCMOS CPLD (data taken with 32 up/down, loadable 16-bit counters at 3.3V, 25C).
140 120 100
*
*
* * * * * *
Typical ICC (mA)
80 60 40 20 0 0 20 40 60 80 100 120 140 160
Frequency (MHz)
DS024_01_112700
Figure 1: XCR3512XL Typical ICC vs. Frequency at VCC = 3.3V, 25C Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25C Frequency (MHz) Typical ICC (mA) 0 TBD 1 TBD 10 TBD 20 TBD 40 TBD 60 TBD 80 TBD 100 TBD 120 TBD 140 TBD
(c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS081 (v1.2) September 4, 2001 Advance Product Specification
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XCR3512XL: 512 Macrocell CPLD
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DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol VOH
(2)
Parameter Output High voltage
Test Conditions VCC = 3.0V to 3.6V, IOH = -8 mA VCC = 2.7V to 3.0V, IOH = -8 mA IOH = -500 A
Min. 2.4 2.0(3) 90% VCC -10 -10 5 -
Max. 0.4 10 10 100 TBD TBD 8 12 10
Unit V V V V A A A mA mA pF pF pF
VOL IIL IIH ICCSB ICC CIN CCLK CI/O
Output Low voltage Input leakage current I/O High-Z leakage current Standby current Dynamic current(4,5) capacitance(6)
IOL = 8 mA VIN = GND or VCC VIN = GND or VCC VCC = 3.6V f = 1 MHz f = 50 MHz
Input pin
f = 1 MHz f = 1 MHz f = 1 MHz
Clock input capacitance(6) I/O pin capacitance (6)
Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. See Table 1, Figure 1 for typical values. 5. This parameter measured with a 16-bit, loadable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing. 6. Typical values, not tested.
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XCR3512XL: 512 Macrocell CPLD
100 90 80 70 60 IOL (3.3V)
mA
50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (2.7V) IOH (3.3V)
Volts
DS012_10_041901
Figure 2: Typical I/V Curve for the XPLA3 Family
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-7 Symbol TPD1 TPD2 TCO TSUF TH(4) TWLH TR TL
(4) (4) (4) (4)
-10 Max. Min. 3.5 6.5 0 4.0 6.0 Max. 9.0 10.0 5.8 20 20 97 TBD TBD 11.0 11.0 10.3 11.0 Min. 3.5 7.9 0 5.0 7.5 -
-12 Max. 10.8 12.0 6.9 20 20 77 TBD TBD 13.0 13.0 12.4 13.0 Unit ns ns ns ns ns ns ns ns ns ns MHz s s ns ns ns ns
Parameter Propagation delay time (single p-term) Propagation delay time (OR Setup time fast Setup time Hold time Global Clock pulse width (High or Low) P-term clock pulse width Input rise time Input fall time array)(3) Clock to output (global synchronous pin clock)
Min.
TSU(4)
TtPLH
(4)
fSYSTEM TINIT(4) TPOE(4) TPOD TPCO TPAO
(4) (4)
(4) (4)
Maximum system frequency Configuration time(5) ISP initialization time P-term OE to output enabled P-term OE to output disabled(6) P-term clock to output P-term set/reset to output valid
TCONFIG
(4)
Notes: 1. Specifications measured with one output switching. 2. See XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 12 mA at 3.6V. 6. Output CL = 5 pF.
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XCR3512XL: 512 Macrocell CPLD
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Internal Timing Parameters(1,2)
-7 Symbol
Buffer Delays
-10 Max. Min. Max. Min.
-12 Max. Unit
Parameter
Min.
TIN TFIN TGCK TOUT TEN TLDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI1 TLOGI2 TF TLOGI3 TUDA TSLEW
Input buffer delay Fast input buffer delay Global clock buffer delay Output buffer delay Output buffer enable/disable delay
-
3.3 3.8 1.3 3.2 5.2
-
4.0 3.8 1.5 3.8 6.0
ns ns ns ns ns
Internal Register and Combinatorial Delays
Latch transparent delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output delay Register async. S/R to output delay Register async. recovery Internal logic delay (single p-term) Internal logic delay (PLA OR term)
1.0 5.5 2.5 4.5 -
1.6 1.3 2.0 7.0 2.5 3.5
1.2 6.7 3.0 5.5 -
2.0 1.6 2.2 8.0 3.0 4.2
ns ns ns ns ns ns ns ns ns ns
Feedback Delays
ZIA delay
-
4.5
-
6.0
ns
Time Adders
Fold-back NAND delay Universal delay Slew rate limited delay
-
2.5 2.8 5.0
-
3.0 3.5 6.0
ns ns ns
Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See XPLA3 family data sheet (DS012) for timing model.
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XCR3512XL: 512 Macrocell CPLD
Switching Characteristics
VCC
S1 Component R1 R2 C1 VOUT R2 C1 Values 390 390 35 pF
R1 VIN
Measurement TPOE (High) TPOE (Low) TP
S1 Open Closed Closed
S2 Closed Open Closed
Note: For TPOD, C1 = 5 pF S2
DS013_03_050200
Figure 3: AC Load Circuit
7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6.3 1 2 4 8 16
+3.0V 90%
(ns)
10% 0V
TR
1.5 ns
TL
1.5 ns
Number of Adjacent Outputs Switching
DS024_04_11800
Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
DS017_05_042800
Figure 4: Derating Curve for TPD2
Figure 5: Voltage Waveform
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Pin Descriptions
Table 2: XCR3512XL User I/O Pins PQ208 Total User I/O Pins 180 FT256 212 FG324 260
Table 3: XCR3512XL I/O Pins (Continued) Function Block 2 2 2 Macrocell 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PQ208 4 6 203 202 201 199 198 7 8 9 10 11 FT256 D14 D15 A14 E11 A13 D12 B13 C12 E13 C16 F12 D16 E14 E15 FG324 F19 E21 E22 B19 A20 C18 B18 A19 D17 A18 C17 F20 F21 F22 G19 G20 G21 G22 H20
Table 3: XCR3512XL I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 PQ208 208 207 206 205 204 1 2 3 FT256 C14 D13 A15 B15 B14 C13 E12 A16 C15 B16 FG324 C21 C20 B22 B21 A22 A21 B20 C19 D20 C22 D21 D22 E20
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
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XCR3512XL: 512 Macrocell CPLD Table 3: XCR3512XL I/O Pins (Continued) FG324 B17 A17 D16 C16 B16 A16 C15 B15 H21 H22 J19 J20 J21 J22 K19 K20 A15 D14 C14 Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 Macrocell 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 PQ208 189(1) 188 187 18 19 20 21 22 24 51 49 FT256 C10(1) A9 D9 G13 F16 G14 G16 H13 H12 P16 N14 R16 FG324 B14(1) A14 D13 C13 B13 K21 K22 L19 L20 L21 L22 M21 M20 AA21 AB22 AA22 Y20 -
Table 3: XCR3512XL I/O Pins (Continued) Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 PQ208 197 196 195 194 193 12 13 15 16 17 192 190 FT256 A12 D11 A11 E10 B12 C11 F13 E16 F15 G12 F14 G15 B11 D10 A10
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XCR3512XL: 512 Macrocell CPLD Table 3: XCR3512XL I/O Pins (Continued) Function Block 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 Macrocell 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 PQ208 48 47 46 45 52 53 54 55 56 57 44 43 42 FT256 M13 P15 L12 N16 N13 R15 M12 T16 P14 T15 P13 M14 M16 L13 N15 FG324 Y21 W20 W21 Y22 AB21 Y19 AA20 AB20 Y18 AA19 AB19 W17 W22 V20 V21 U19 Table 3: XCR3512XL I/O Pins (Continued) Function Block 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13 13 13 13 Macrocell 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 PQ208 40 39 38 58 59 60 61 62 37 36 35 FT256 M15 L16 K12 R14 N12 T14 M11 R13 P12 T13 L15 K13 K16 FG324 V22 U20 U21 U22 Y17 AA18 AB18 AA17 AB17 W16 Y16 AA16 T19 T20 T21 T22 -
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XCR3512XL: 512 Macrocell CPLD Table 3: XCR3512XL I/O Pins (Continued) FG324 R20 R21 R22 P19 AB16 Y15 AA15 AB15 W14 Y14 AA14 AB14 P20(1) P21 P22 N19 N21 N22 M22 Function Block 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 Macrocell 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 PQ208 25 70 71 73 76 77 78 157 158 159 160 161 156 155 FT256 H15 T11 R10 P10 T10 N9 R9 P9 B1 B2 C3 D4 A2 A1 B3 C1 D3 FG324 M19 W13 Y13 AA13 AB13 W12 AA12 AB12 Y11 C3 A2 B3 C4 B4 C5 B5 A3 D3 B2
Table 3: XCR3512XL I/O Pins (Continued) Function Block 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 Macrocell 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PQ208 34 33 31 64 65 66 67 68 69 30(1) 29 28 27 26 FT256 K14 K15 L14 J16 N11 R12 T12 R11 M10 P11 N10 J13(1) J15 J14 H16 H14
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XCR3512XL: 512 Macrocell CPLD Table 3: XCR3512XL I/O Pins (Continued) Function Block 18 18 18 18 18 18 18 18 18 18 18 18 18 18 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 Macrocell 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 PQ208 154 153 151 150 162 163 164 166 167 149 148 147 FT256 C2 F5 D1 E4 C4 A3 D5 B4 E6 A4 C5 D2 E3 E1 FG324 B1 C2 C1 E3 D2 D1 A4 D6 A5 C6 B6 A6 D7 C7 F4 F3 E2 E1 Table 3: XCR3512XL I/O Pins (Continued) Function Block 20 20 20 20 20 20 20 20 20 20 20 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 22 22 22 22 22 22 22 22 Macrocell 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 PQ208 146 145 144 168 169 170 171 172 142 141 140 FT256 F4 F1 G5 B5 D6 A5 C6 B6 E7 A6 E2 F3 F2 FG324 F2 F1 G4 G3 B7 A7 C8 B8 A8 D9 C9 B9 G2 G1 H3 H2 -
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XCR3512XL: 512 Macrocell CPLD Table 3: XCR3512XL I/O Pins (Continued) FG324 H1 J4 J3 J2 A9 D10 C10 B10 A10 D11(1) C11 B11 J1 K4 K3 K2 Function Block 24 24 24 24 24 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 26 26 26 26 26 26 26 26 26 26 26 26 26 26 Macrocell 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PQ208 133 132 105 106 108 109 110 111 104 103 102 FT256 J1 J3 P2 P3 T1 N3 R1 M4 M5 N4 R2 T2 P4 FG324 K1 L1 L4 L3 AA1 Y3 Y2 W3 Y1 W2 W1 V3 AB1 AA2 AB2 AA3 Y4 AB3
Table 3: XCR3512XL I/O Pins (Continued) Function Block 22 22 22 22 22 22 22 22 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 24 24 24 24 24 24 24 24 24 24 24 Macrocell 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 PQ208 139 138 173 175 176(1) 177 178 137 136 135 FT256 G4 G1 G3 D7 B7 C7 C8 A7(1) D8 B8 H1 H4 G2 H3 -
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XCR3512XL: 512 Macrocell CPLD Table 3: XCR3512XL I/O Pins (Continued) Function Block 26 26 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 29 Macrocell 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 PQ208 101 100 112 113 114 115 117 118 99 98 97 96 95 93 119 FT256 R3 N5 P1 L5 N2 M3 L4 M2 T3 M6 R4 P5 T4 N6 R5 L2 FG324 AA4 Y5 U4 V2 V1 U3 U2 U1 T3 T2 AA5 AB4 W6 AB5 Y6 AA6 AB6 W7 T1 Table 3: XCR3512XL I/O Pins (Continued) Function Block 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 31 31 31 31 Macrocell 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 PQ208 120 121 122 123 124 92 91 90 89 88 87 126 127(1) 128 FT256 M1 K5 L3 K4 L1 T6 T5 M7 R6 N7 T7 P6 K2 K3 K1(1) J4 FG324 R3 R2 R1 P4 P3 P2 P1 Y7 AA7 AB7 Y8 AA8 AB8 W9 Y9 N4 N3 N2(1) N1
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XCR3512XL: 512 Macrocell CPLD
Table 3: XCR3512XL I/O Pins (Continued) Function Block 31 31 31 31 31 31 31 31 31 31 31 31 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Notes: 1. JTAG pins.
Table 4: XCR3512XL Global, JTAG, Port Enable, Power, and No Connect Pins FG324 M4 M3 M2 L2 AA9 AB9 W10 Y10 AA10 AB11 W11 AA11 No Connects GND Pin Type IN0 / CLK0 IN1 / CLK1 IN2 / CLK2 IN3 / CLK3 TCK TDI TDO TMS PORT_EN Vcc PQ208 181 182 183 184 30 176 189 127 116(1) 5, 23, 41, 63, 74, 83, 85, 107, 125, 143, 165, 179, 186, 191 FT256 B9 A8 C9 B10 J13 A7 C10 K1 N1(1) FG324 C12 B12 D12 A12 P20 D11 B14 N2 T4(1)
Macrocell 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PQ208 129 130 131 86 84 81 80 79
FT256 J2 J5 H2 R7 P7 T8 N8 R8 P8 T9
A11, A13, E8, E9, F7, F8, F9, F10, D8, D15, H4, H19, J10, G6, G11, H5, J11, J12, H6, H11, J6, J13, K9, J11, J12, K6, K14, L9, K11, L7, L8, L9, L10, M8, L14, M1, M9, M14, N9, M9 N14, N20, P10, P11, P12, P13, R4, R19, W8, W15, Y12, AB10
14, 32, 50, E5, F6, F11, D4, D5, D18, D19, E4, 72, 75, 82, G7, G8, G9, 94, 134, 152, G10, H7, H8, E19, J9, J14, K10, K11, 174, 180, H9, H10, J7, K12, K13, 185, 200 J8, J9, J10, L10, L11, K7, K8, K9, L12, L13, K10, L6, L11 M10, M11, M12, M13, N10, N11, N12, N13, P9, P14, V4, V19, W4, W5, W18, W19 A1
Notes: 1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet for full explanation.
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XCR3512XL: 512 Macrocell CPLD
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Ordering Information
Example: XCR3512XL -10 PQ 208 C
Device Type Speed Grade Temperature Range Number of Pins Package Type
Device Ordering Options
Speed -12 -10 -7 12 ns pin-to-pin delay 10 ns pin-to-pin delay 7.5 ns pin-to-pin delay PQ208 FT256 FG324 Package 208-pin Plastic Quad Flat Package 256-ball Fineline BGA Package 324-ball Fineline BGA Package Temperature C = Commercial I = Industrial TA = 0C to +70C VCC = 3.0V to 3.6V TA = -40C to +85C VCC = 2.7V to 3.6V
Component Compatibility
Pins Type Code
XCR3512XL
208 Plastic PQFP PQ208 -7 -10 -12 C C, I C, I
256 Plastic FBGA FT256 C C, I C, I
324 Plastic FBGA FG324 C C, I C, I
Revision History
The following table shows the revision history for this document Date 04/11/01 04/19/01 09/04/01 Version 1.0 1.1 1.2 Initial Xilinx release. Updated Typical I/V curve, Figure 2: added voltage levels. Updated AC Electrical: added TINIT spec.; Internal Timing Parameters; added -12 industrial temperature. Revision
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